Because there is a path that exists for EVERY capacitor exclusively in the circuit.
I.e. : there is a path through exclusively capacitor A
There is a path through exclusively capacitor B
There is a path through exclusively capacitor C
This path argument explains the flow of charge laws fitting a parallel configuration, but is it consistent with a voltage loop law?
To find out, label the points 1 through 4, with 1 and 2 on either side of capacitor A...2 and 3 on either side of capacitor B...and 3 and 4 on either side of capacitor C. The question? What voltage level is each of these numbered nodes at?
Node 1: You immediately see a direct connection to node O. Hence voltage O.
Node 2: the bypass loop around capacitors B and C leaves it directly connected to node P. Hence voltage P.
Node 3: the bypass loop around capacitors A and B leaves it directly connected to node O. Hence voltage O.
Node 4: You immediately see a direct connection to node P. Hence voltage P.
Label each node with the voltage of the node. Now realize that ALL capacitors connect a node of voltage O to a node of voltage P, without ever passing through another capacitor. This is why the capacitors are equivalently arranged to being in parallel.
"Lesson here: don't draw screwy diagrams! :-)"
I couldn't agree more. This is precisely what they are trying to teach you, is how to resolve a screwy diagram.