why the NAND gate is not preferred in RTL( resistor transistor logic)?

Question

why the NAND gate is not preferred in RTL( resistor transistor logic)?

Answer 1

See the attached link,

Scroll down to the fourth photo showing a stacked Nand RTL circuit.



The saturation current of the transistors are typically about 0.3V, which means that if you stack two transistors in series as shown in the link photo, the series voltage is about 0.6V, which is at the Vbe turnon voltage. So if you stack three transistors, the saturation would be 1.8V or so, and the transistors could not turn on.



A solution to this problem is shown by adding diodes to the inputs shown in the second link, but this is diode transistor logic DTL, not RTL.





- - - - - -SNIP - - - - - -

The problem with this NAND circuit stems from the fact that transistors are not ideal devices. Remember that 0.3 volt collector saturation voltage? Ideally it should be zero. Since it isn't, we need to look at what happens when we "stack" transistors this way. With two, the combined collector saturation voltage is 0.6 volt -- only slightly less than the 0.65 volt base voltage that will turn a transistor on.



If we stack three transistors for a 3-input NAND gate, the combined collector saturation voltage is 0.9 volt. This is too high; it will promote conduction in the next transistor no matter what. In addition, the load presented by the upper transistor to the gate that drives it will be different from the load presented by the lower transistor. This kind of unevenness can cause some odd problems to appear, especially as the frequency of operation increases. Because of these problems, this approach is not used in standard RTL ICs.

- - - - - -SNIP - - - - - -

Answer 2

Rtl Nand Gate

Answer 3

purely the very least complicated units actual use 7400 or comparable gates. 7400 good judgment has long previous the way of vinyl information and steam engines. at present you're able to desire to earnings VHDL or Verilog, and so on and write code, specially equations, that describe the best judgment you like, and permit the compiler application in high-quality condition it to a suited programmable device (~FPGA) and simulate the effect to be constructive it is going to artwork on the mandatory velocity. The compiler will additionally manage fan in/out if mandatory, besides the very undeniable fact that the IO modern of a few FPGA is programmable. the priority with fan-in/out become that it become ineffective adequate to think of that good judgment could continuously be TTL and it predates sturdy transmission line (aka extreme velocity digital) layout, so very quickly hardware layout dropped the thought as greater hardship than it become nicely worth. extremely, an engineer will look up the enter and output currents if mandatory. whilst you're utilising a 50 Ohm hint with a 5 Volts then you fairly prefer 100mA. for this reason little or no good judgment makes use of 5V to any extent further. for 2.5V into 50 Ohms is merely 50mA, ie a million/4 the means. CMOS inputs are mandatory capacitors so the mandatory force relies upon on the fee. At extreme speeds, the inputs are a minor concern whilst in comparison with hint impedance, and any style of bus is prevented in prefer of element to point. it is consumer-friendly for multiple output buffer chips to be utilized so as that no busing is needed and any good judgment required is the two inner to LSI units or basic glue good judgment. something basic adequate to be outfitted with a dozen TTL chips may be programmed right into a $a million.50 CPLD and in high-quality condition on a postage stamp length PCB extremely of one the size of a letter.